Power up reset circuit with threshold voltage shift protection

ABSTRACT

The reset circuit includes a first current mirror coupled to a first terminal of a power supply. A second current mirror is coupled to a second terminal of the power supply. First and second switches couple the first current mirror to the second current mirror. A threshold detector provides a first signal when a current differential between the first and second current mirrors exceeds a predetermined threshold. A first shunt shunts the first current mirror to the first terminal. A second shunt shunts the second current mirror to the second terminal. Buffering circuitry controls the first and second switches and the first and second shunts in response to the first signal. The buffering circuitry further provides a buffered reset signal from the first signal. The buffered reset signal transitions from a first level to a second level in response to the first signal. The switches and shunts reduce the biases on the threshold detector and current mirrors.

FIELD OF THE INVENTION

This invention relates to power up reset circuitry. In particular, thisinvention relates to an improved power up reset circuit for electroniccircuitry.

BACKGROUND OF THE INVENTION

When power is initially applied to systems having electrical circuitry,various components of the system typically power up in an unknown state.After applying power, a reset signal may be applied to such componentsto reset them to a known state.

Of particular importance is when the system components should be reset.Resetting system components as soon as possible during the power upprocess is desirable for at least two reasons. First, to minimize timebetween application of power and when the system is functional, thereset should be initiated during the power up process. Second, byperforming a reset before full power levels are achieved, hazardousconditions that could damage system components can be avoided.

In order to reduce the time required to bring the system up to fullfunctionality from the time at which the power was first applied, thereset function is typically initiated during the power up process.Although the steady state output of a power supply might have a givennominal level, time is required for the steady state output levels tobecome available throughout the system when the power supply is firstactivated. Because initializing and resetting system components alsotakes some amount of time, the initialization and resetting processshould preferably take place as soon as possible after power isinitially applied to the system. This permits initialization and resetfunctions to execute concurrently or at least begin during the power upprocess. This in turn helps to minimize the total amount of timerequired for power up, initialization, and reset.

Failure to reset system components in a timely manner may result incatastrophic failure for the system. For example, in a computer system,buses are typically used to communicate data, address, and controlinformation between various system components. These components usuallyinclude a bus driver to transform electrical signals from the componentinto voltage and current levels required for bus communication. Ideallythe bus drivers operate in a tri-state mode during the power up processso that none of them are attempting to send conflicting signals on thebus. When the power is first applied, however, one bus driver mayinitialize to a state in which it attempts to drive one value onto thebus while a second driver is attempting to drive another value on thebus. These different values are physically represented by opposingelectrical values. Thus one driver may be attempting to drive a voltageapproaching available power supply levels onto the bus while another isattempting to drive the bus to a signal ground. This hazardous conditioncan permanently damage the bus, a component coupled to the bus, or oneor more bus drivers. To avoid such an event, system components aretypically reset to a known state before the power supply reaches fulloutput levels. Thus avoiding a risk of catastrophic failure is anotherreason for resetting system components during the power-up process andnot afterwards.

A power up reset circuit is used to provide a reset signal to systemcomponents. The system components respond by resetting themselves to aknown state after receipt of the reset signal. Some components requireat least some minimal power supply level so that they can be reset to aknown state. This means that the reset signal will not be effectiveuntil the power supply reaches at least this minimal level. The resetsignal should be provided, however, while the power available to thesystem is still relatively low in order to avoid hazardous conditionssuch as that provided in the example above. Furthermore, the resetsignal should be removed at some point during the power up process sothat system can proceed with any necessary initialization proceduresafter the reset.

FIG. 1 illustrates a block diagram for a system using a reset circuit.FIG. 2 illustrates timing and voltage relationship between VCC and areset signal. Referring to FIG. 1 and FIG. 2, the power supply output isprovided to system 100 at time 210 by closing switch 110. The powersupply output transitions over a discrete period of time to the nominaloperating voltage as illustrated by power supply voltage level 220.Closing switch 110 couples the power supply output to the various systemcomponents such as microprocessor 130. Switch 110 couples the powersupply output to power up reset circuit 120. In one prior art power upreset circuit, the reset signal is generated upon or shortly afterinitial application of the power supply voltage. FIG. 2 illustratesreset signal 230 being asserted at time 212. The reset circuit iscoupled to provide the reset signal to the various system components(e.g., microprocessor 130) that need it. The reset signal remains on(i.e., asserted) until the power supply has reached a predeterminedlevel. At this predetermined level (i.e., 240), the reset circuitdeasserts the reset signal. The predetermined level at which the resetsignal transitions from one state to the other state is referred to asthe trigger point or trip point. In accordance with goals of 1)minimizing the time required for power up, reset, and initialization;and 2) avoiding the risk of catastrophic failure; the reset signalshould be asserted upon or shortly after power is turned on and thetrigger point is typically set to be somewhere between the minimal powersupply level required for resetting and the power supply level beyondwhich catastrophic failure may result.

One prior art power up reset circuit uses the threshold voltage (V_(t))of one or more transistors in order to set or determine the triggerpoint level. Such a power up reset circuit is described in U.S. Pat. No.5,111,067 of Wong, et al. One disadvantage of this prior art circuitryis that the threshold voltages can permanently shift over the course ofcontinued power up and power down cycles such that the trigger pointmoves. The shifting of the trigger point can cause a reset signal to begenerated too soon, too late, or even not at all. Thus decreasing thesensitivity of a power up reset circuit to shifting threshold voltagesis desirable.

SUMMARY OF THE INVENTION

An improved power up reset circuit is provided. The reset circuit isdesigned such that the trigger point for the reset signal issubstantially independent of the shifting of transistor thresholdvoltages which may occur over the course of a number of power up andpower down cycles.

The improved power up reset circuit reduces the likelihood of athreshold voltage shift through the use of shunts and switches. Theshunts and switches are used to reduce biases across critical componentsafter the trigger point has been reached.

The reset circuit includes a first current mirror coupled to a firstterminal of a power supply. A second current mirror is coupled to asecond terminal of the power supply. First and second switches couplethe first current mirror to the second current mirror. A thresholddetector provides a first signal when a current differential between thefirst and second current mirrors exceeds a predetermined threshold. Afirst shunt shunts the first current mirror to the first terminal. Asecond shunt shunts the second current mirror to the second terminal.Buffering circuitry controls the first and second switches and the firstand second shunts in response to the first signal. The bufferingcircuitry further provides a buffered reset signal from the firstsignal. The buffered reset signal transitions from a first level to asecond level in response to the first signal.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 illustrates a block diagram of a reset circuit and computersystem components requiring a reset signal.

FIG. 2 illustrates one embodiment of the relationship between powersupply voltage levels and a reset signal.

FIG. 3 illustrates a prior art power up reset circuit.

FIG. 4 illustrates an improved reset circuit with protection fromthreshold voltage shifts.

DETAILED DESCRIPTION

FIG. 3 illustrates one embodiment of reset circuit 120 as illustrated inFIG. 1. Reset circuitry 300 of FIG. 3 is described in U.S. Pat. No.5,111,067 of Wong, et al., incorporated herein by reference. FIG. 4illustrates an improvement of the circuitry of FIG. 3.

Referring to FIGS. 1 and 3, assume that switch 110 is open and that nopower is being supplied to reset circuit 120 or to the other components.Under these circumstances, latching node PWR1 is in the powered-downstate (i.e., approximately zero volts).

When power is initially applied by closing switch 110, transistors MP1and MP3 are among the first to gradually turn on. This forces theinverter comprising transistors MP5 and MN5 to maintain the PWR3 node atapproximately zero volts. The circuitry is designed so that the voltageat PWR1 remains sufficiently low so that MP1 stays on while PWR2 issufficiently high to keep transistor MP5 off, thus maintaining PWR3 atapproximately zero volts during the gradual turn on of transistors MP1and MP3.

MP4 is on such that node PWR4 has sufficient potential to keep MN2 on.This results in a current path through transistors MP3-MP4-MN2. Becauseof the MP3-MP4-MN2 current path, the voltage at node PWR2 increases at aslower rate than the initial rise in supply voltage, VCC. When thedifference between the supply voltage and the voltage at node PWR2becomes large enough (as determined by circuitry design and thethreshold voltage of MP2), transistor MP2 will turn on. Thus transistorMP2 is a "threshold detector" for this voltage differential. TransistorMP2 is critical for selecting the trigger or trip point of the resetcircuitry.

The trigger point is determined by the threshold voltage of MP2 (i.e.,V_(tMp2)) and the relative gain differential between the MN1 and MN2pair and the MP1 and MP2 pair of transistors. The turning on of MP2 inturn raises node PWR1 high. Transistors MP2-MP3-MN3 become latched suchthat PWR2 is latched low. The rest of the circuitry serves as buffers ordrivers. Once PWR2 is latched low the reset signal at output node 380 isdeasserted. Up until this point the reset signal has been asserted(i.e., following VCC).

An enable control 390 is provided to permit disabling the resetcircuitry. The reset circuit can provide a reset signal other than VCConly when enabled by the enable control. The reset circuitry is designedfor an active low enable control. This is expressed symbolically as ENor EN# as illustrated in FIG. 3. If enable control 390 is high,transistor MN7 will turn on pulling PWR6 to ground. Furthermore, ifenable control 390 is high, transistor MP7 disables inverter MP8-MN8such the node PWR6 is unaffected by the reset of the reset circuitry.Due to the inverter formed by transistors MP9 and MN9, this means thatoutput node 380 will reflect substantially VCC as long as the enablecontrol signal is high independently of the rest of the circuitry.Alternatively, if a low signal is applied to enable control 390, nodePWR6 will be controlled by the rest of the circuitry such that a non-VCCreset signal can be provided by output node 380.

As long as PWR1 is latched high, the latching circuit will provide adeasserted reset signal at output node 380. Resistor R1 is provided tofacilitate leakage of charge from node PWR1 in the event of a powersupply interruption so that the latching circuit can immediately switchfrom the latched state to the unlatched stated. This permits properoperation of the reset signal after power supply interruptions of shortduration.

One disadvantage of this prior art circuit is that the thresholdvoltages of transistors MN1, MP2, and MP3 can become permanently shiftedafter a number of power-up and power down cycles. This shifting causes amismatch in the current mirror comprising MP1 and MP3 and in the currentmirror comprising MN1 and MN2. In other words, the drain-to-gate biasesapplied to these transistors can cause threshold voltage (V_(t)) shiftsso that the next time the device is powered up, the trigger point occursat a different VCC level. The trigger point tended to shift to a greaterVCC level thus preventing proper low voltage operation of the system.

FIG. 4 illustrates one embodiment of the improved circuitry. Inparticular, transistors MN1A, MP2A, MP3A, MN4A, and MP10 have been addedto help reduce the biases on transistors MN1, MP2, and MP3.

As compared with FIG. 3, the MP6-MN6 inverter has been removed so thatthe RESET signal is now RESET when referenced to the prior art circuitof FIG. 3. (RESET is shown as RESET# in FIG. 4). As stated previously,the MP6-MN6 inverter served primarily as a buffer or driver which may ormay not be necessary depending upon what the output requirements are onthe reset circuitry. Because the MP6-MN6 inverter has been removed inthis embodiment, the output of the reset circuit actually transitions toa high level (approaching VCC) once the trigger point is reached.

As with the prior art circuit, when VCC reaches the trigger point, nodePWR1 transitions from a low state to a high state. The level at PWR1 isinverted by inverter MP3A-MN3 and again by inverter MPS-MN5 so that nodePWR3 is also high. Assuming that the reset signal is enabled (EN# 490 islow), node PWR3 is inverted by inverter MP8-MN8 such that node PWR6transitions to a low level. Node PWR6 is inverted by inverter MP9-MN9such that the RESET# signal transitions from a low level to VCC once VCCreaches the trigger point.

In one embodiment, the reset circuitry is implemented with field effecttransistors using complementary metal oxide semiconductor (CMOS)technology. Functionally, MP1 and MP3 act as a PMOS (i.e., P-type MOS)current mirror (the upper current mirror). MN1 and MN2 serve as an NMOS(i.e., N-type) current mirror (the lower current mirror). Transistor MP2serves as the threshold detector and determines when the currentdifferential between the upper and lower current mirrors exceeds apredetermined level (corresponding to the VCC trigger point). InvertersMP3A-MN3, MP5-MN5, MP8-MN8, and MP9-MN9 serve primarily as buffers ordrivers. The number of buffer or driver stages may vary dependent uponthe reset signal output requirements. The only constraint on the numberand placement of inverters is that node PWR3 must follow node PWR1 andnode PWR6 must be the logical complement of PWR3 so that the appropriatecontrol signals are provided to switches MN1A, MP4, MP2A, and MP10.

Switches are used to reduce the biases which can lead to shiftedthreshold voltages on components critical to determining the trigger 5point. After the reset signal is latched, the switches decouple theupper current mirror circuitry from the lower current mirror circuitry.The bias across transistors comprising the upper current mirror isreduced by shunting the upper current mirror to VCC. The bias acrosstransistors comprising the lower current mirror is reduced by shuntingthe lower current mirror to ground.

Transistors MN1A and MP4 serve as switches to decouple the upper currentmirror from the lower current mirror. In particular, MN1A and MP4decouple the drains of MN1 and MN2 from approximately VCC. After thereset signal is latched node PWR6 is at a low level and nodes PWR1 andPWR3 are at a high level. Node PWR6 is coupled to the gate of MN1A, sothat the drain of MN1A is decoupled from node PWR1 after the resetsignal is latched. The high level at node PWR3 is applied to the gate ofMP4, so that the drain of MN2 is decoupled from VCC after the resetsignal is latched. Thus once the trigger point is reached, switches MN1Aand MP4 decouple the lower current mirror from the upper current mirror.

Transistors MN4A and MN4 serve as switches to shunt the lower currentmirror to ground after the reset signal is latched so that there issubstantially no bias across the lower current mirror. Now that thereset circuit is providing the latched reset signal, node PWR6 is lowand node PWR3 is high. Transistor MN4A is controlled by node PWR3 toshunt the drain of MN1 to ground when the reset signal is latched.Transistor MN4 is controlled by node PWR3 to shunt the drain of MN2 toground when the reset signal is latched. Thus MN4 and MN4A collectivelyserve as shunting circuitry for the lower current mirror. The lowercurrent mirror is shunted to ground to reduce the bias across thetransistors comprising the lower current mirror. This reduction in bias,in turn, substantially reduces the likelihood of a threshold voltageshift for the components of the lower current mirror.

With respect to the upper current mirror, transistors MP2A and MP10serve as shunt circuitry to reduce potentially harmful biases. Inparticular, node PWR6 controls MP10 to shunt the gate of MP2 and thedrain of MP3 to VCC once the reset signal latches. This substantiallyreduces the bias across MP2 and MP3. Assuming node PWR1 is approachingVCC, the drain, gate, and source of transistors MP2 and MP3 are exposedto approximately the same potential. Thus any bias across transistorsMP2 and MP3 has been substantially reduced. The reduction in bias helpsto eliminate shifting of the threshold voltages of transistor MP3 andthreshold detector MP2. This in turn helps to improve the stability ofthe trigger point after numerous power-up cycles.

Transistor MP2A helps to keep PWR1 high once the reset signal islatched. Because node PWR6 is low, MP2A will short PWR1 to VCC. MP2A maysuffer from the threshold voltage shifting described above due to thebias across it. MP2A, however, is intended to be a "sacrificial" device.MP2A is serving only as a switch or shunt instead of as part of thecurrent mirror circuitry for the latch. Thus the threshold voltage ofMP2A is not critical to the trigger point determination.

In one embodiment this power up reset circuit is integrated within amicroprocessor to provide the reset signal to the various components ofthe microprocessor and/or system components external to themicroprocessor. In another embodiment the power up reset circuit isexternal to the microprocessor.

In the preceding detailed description, the invention is described withreference to specific exemplary embodiments thereof. Variousmodifications and changes may be made thereto without departing from thebroader spirit and scope of the invention as set forth in the claims.The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A reset circuit comprising:a first currentmirror; a second current mirror; a threshold detector coupled to providea first signal in response to a detected current differential betweenthe first and second current mirrors; a first shunt coupled to shunt thefirst current mirror in accordance with the first signal such that afirst current mirror bias is substantially zero; and a second shuntcoupled to shunt the second current mirror in accordance with the firstsignal such that a second current mirror bias is substantially zero. 2.The reset circuit of claim 1 wherein the first shunt includes circuitryto shunt the threshold detector such that a threshold detector bias issubstantially zero.
 3. The reset circuit of claim 1 further comprising:afirst switch to couple the first current mirror to the second currentmirror in accordance with the first signal; and a second switch tocouple the first current mirror to the second current mirror inaccordance with the first signal.
 4. The reset circuit of claim 3further comprising:buffering circuitry providing a buffered reset signalfrom the first signal, the buffering circuitry controlling the first andsecond switches and the first and second shunts in response to the firstsignal, the buffered reset signal transitioning from a first level to asecond level in response to the first signal.
 5. A reset circuitcomprising:a first current mirror coupled to a first terminal of adirect current power supply; a second current mirror coupled to a secondterminal of the direct current power supply; a first switch to couplethe first current mirror to the second current mirror; a second switchto couple the first current mirror to the second current mirror; athreshold detector, wherein the threshold detector provides a firstsignal when a current differential between the first and second currentmirrors exceeds a predetermined threshold; a first shunt to shunt thefirst current mirror to the first terminal; a second shunt to shunt thesecond current mirror to the second terminal; and buffering circuitryproviding a buffered reset signal from the first signal, the bufferingcircuitry controlling the first and second switches and the first andsecond shunts in response to the first signal, the buffered reset signaltransitioning from a first level to a second level in response to thefirst signal.
 6. The reset circuit of claim 5 where in the first shuntincludes circuitry to shunt the threshold detector such that a thresholddetector bias is substantially zero.
 7. The reset circuit of claim 5wherein the buffering circuitry includes at least one inverter.
 8. Thereset circuit of claim 5 wherein the buffering circuitry includes anenable control such that the buffered reset signal transitions from thefirst level to the second level only if the enable control is enabled.9. The reset circuit of claim 5 implemented in complementary metal oxidesemiconductor (CMOS) technology.
 10. The reset circuit of claim 5wherein the first and second shunts comprise field effect transistors.11. The reset circuit of claim 5 wherein the first and second currentmirrors comprise field effect transistors.
 12. A system comprising:atleast one component requiring a reset signal; a reset coupled to thecomponent, circuit comprising:a first current mirror coupled to a firstterminal of a power supply; a second current mirror coupled to a secondterminal of the direct current power supply; a first switch to couplethe first current mirror to the second current mirror; a second switchto couple the first current mirror to the second current mirror; athreshold detector, wherein the threshold detector provides a firstsignal when a current differential between the first and second currentmirrors exceeds a predetermined threshold; buffering circuitry providinga buffered reset signal to the at least one component, the bufferedreset signal generated from the first signal, the buffering circuitrycontrolling the first and second switches to decouple the first andsecond current mirrors in response to the first signal, the reset signalbuffered transitioning from a first level to a second level in responseto the first signal; a first shunt controlled by the buffering circuitryto shunt the second current mirror to the second terminal in response tothe first signal; and a second shunt controlled by the bufferingcircuitry to shunt the first current mirror to the first terminal inresponse to the first signal.
 13. The reset circuit of claim 12 where inthe first shunt includes circuitry to shunt the threshold detector suchthat a threshold detector bias is substantially zero.
 14. The system ofclaim 12 wherein the buffering circuitry includes at least one inverter.15. The system of claim 12 wherein the buffering circuitry includes anenable control such that the reset signal transitions from the firstlevel to the second level only if the enable control is enabled.
 16. Thesystem of claim 12, implemented in complementary metal oxidesemiconductor (CMOS) technology.
 17. The system of claim 12, wherein thefirst and second shunts comprise field effect transistors.
 18. Thesystem of claim 12 wherein the first and second current mirrors comprisefield effect transistors.